1. Field of the Invention
The present invention relates to a data processing apparatus and method, and in particular to techniques for performing arbitration between a plurality of transfers to be routed over an interconnect circuit of a data processing apparatus.
2. Description of the Prior Art
It is known to provide a data processing apparatus having a plurality of logic elements that are interconnected via an interconnect circuit. Communication between the logic elements occurs via transfers which may be issued from one logic element (referred to herein as the initiator logic element) to another logic element (referred to herein as the recipient logic element) via a path provided by the interconnect circuit.
As data processing apparatus increase in complexity, the number of logic elements provided within the data processing apparatus increase, and this increases the complexity of the interconnect circuit. A typical interconnect circuit may provide a large number of paths for routing transfers between the various logic elements connected to the interconnect circuit, and it is often the case that a number of these paths will include a shared connection.
At any point in time, a shared connection can only be employed to route the transfer data of one transfer, and accordingly arbitration logic is often required in order to arbitrate between multiple requests to transfer data via the interconnect circuit, in order to ensure that for any shared connection in the interconnect circuit, only one initiator logic element is granted the right to use that shared connection at any point in time.
Protocols are typically defined in relation to the interconnect circuit to impose certain requirements on the format of the transfers routed via the interconnect circuit. Often, there is a requirement for some form of handshaking to take place between the initiator logic element and the recipient logic element during the transfer. For example, the AXI interface specification developed by ARM Limited, Cambridge, England, requires that an initiator logic element issues a valid signal when it wishes to initiate a transfer, and that this valid signal is held stable until the completion of a handshake that takes place when a ready signal is asserted by the recipient logic element. Whilst there is a requirement for the valid signal to be held stable until completion of the handshake (a valid signal conforming to this requirement sometimes being referred to as a “sticky” valid signal), the ready signal is not constrained in this way. Instead, the ready signal may be asserted and de-asserted in any clock cycle depending on the internal state of the recipient logic element. Indeed, some recipient logic elements may even wait for a valid signal to be asserted before they issue a ready signal.
The consequence of this is that the arbitration logic associated with the interconnect circuit cannot make use of the ready signal for arbitration. Instead, a typical arbitration scheme would select an initiator logic element to have access to the required path through the interconnect circuit based on that logic element having asserted its valid signal and some measure of that logic element's priority. Once a path has been chosen, the “sticky” valid rule mentioned earlier requires that this path is maintained until the transfer is completed by a handshake. During this potentially unbounded time, that selected path through the interconnect circuit is busy and cannot be used for routing between other logic elements. This can have a significant impact on the throughput of data through the interconnect circuit, particularly in instances where that path incorporates a shared connection.
It would hence be desirable to provide an improved technique for arbitration within a data processing apparatus.